- Pezy insists that workloads require more independence than Lockstep mainstream execution allows
- Pezy SC4S Simulations claim massive efficiency improvements compared to previous generation design
- Chip made on TSMC 5NM with unusually large matrix size
On Hot Chips 2025, a small Japanese company known for unconventional hardware presented its latest project, Pezy SC4S.
Unlike mainstream chip makers who have standardized around a single instruction multiple data design, Pezy Computing continues to pursue more instructions more data (MIMD).
MIMD can be compared to a society of states, prefectures, cities and villages, where each entity deals with a degree of independence rather than following a single central authority.
Selection of architecture and fabrication
MIMD is not a new idea – after all, every modern laptop runs for programming multiple tasks at once, but it has rarely been implemented on a really massive scale involving hundreds or thousands of cores.
The design philosophy assumes that future workloads will not always benefit from locking and that more independent wire handling can be important.
This makes its strategy separate from the direction of most so-called best CPU challengers that dominate the global market.
SC4S is manufactured on the TSMCS 5NM process and is not a small chip with regard to physical footprint.
With a DIE size of about 556 mm2, it is significantly larger than many consumer or work station processors.
However, the emphasis is not on minimizing the silicon area, but rather on testing whether the benefits of massive parallelism outweigh the cost.
The idea that CPUs have hundreds of kernels have been around for a while. Pezy claims that many small, semi-autonomous cores can succeed where centralized approaches are fighting.
In reality, the company is aiming for calculating demand for certain specialized domains to justify this scale, although such an approach can be impractical to the wider consumer adoption.
But what Pezy Computing released are performance simulations rather than final silicon benchmarks, which of course raises questions about how well these claims will have in practice.
Compared to the previous SC3 design, SC4S is expected to deliver more than twice as effective when handling a DGEMM workload.
Meanwhile, simulations of the Smith-Waterman algorithm, used in genome sequence decor, suggest almost a quadrupled increase in performance.
While these numbers are impressive on paper, skepticism remains until independent tests validate them.
Historically, bold projections in semiconductor development do not always have in line with measured results when real hardware ships.
Despite the fact that the SC4s still under development, the company has already moved its attention to a successor.
The work is ongoing on a fifth generation of processor, which is currently called Pezy 5, which is expected to use a 3NM or smaller process.
A release window has been set for 2027, although such long -term schedules in chip development often change due to technical or financial challenges.
Given the scope of the company, industrial observers remain careful about whether the timeline is realistic.
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