- D-Matrix shifts focus from AI training to inferenshardware innovation
- Corsair uses LPDDR5 and SRAM to cut HBM dependence
- Pavehawk combines stacked dram and logic for lower latency
Sandisk and SK Hynix recently signed an agreement to develop “high bandwidth flash”, a NAND-based alternative to HBM designed to bring larger, non-volatile capacity to AI accelerators.
D-Matrix now places itself as a challenger to high-bandwidth memory in the race to speed up workloads to artificial intelligence.
While much of the industry has concentrated on training models using HBM, this company has chosen to focus on AI inferences.
Another approach to the memory wall
Its current design, D-Matrix Corsair, uses a chiplet-based architecture with 256 GB LPDDR5 and 2 GB of SRAM.
Instead of chasing more expensive memory technologies, the idea is that co-package acceleration engines and drama, creating a tighter connection between calculation and memory.
This technology, called D-Matrix Pavehawk, is launched with 3DIMC, which is expected to compete with HBM4 for AI inference with 10x bandwidth and energy efficiency per day. Stack.
The platform is built on a TSMC N5 logic and combined with 3D stacked drama and aims to bring calculation and memory much closer than in conventional layouts.
By eliminating some of the data transfer bottlenecks, D-Matrix suggests that it could reduce both latency and power use.
If you look at your technology trajectory, D-Matrix is required to put more dram-door over logic silicon to push bandwidth and capacity further.
The company claims that this stacked approach can deliver an order of magnitude in performance gains while using less energy for data movement.
For an industry that struggles with the limits of scaling memory interfaces, the proposal is ambitious but remains untested.
It is worth noting that memory innovations about inference accelerators are not new.
Other companies have experimented with densely coupled memory and calculated solutions, including design with built -in controllers or links through interconnection standards such as CXL.
However, D-Matrix is trying to move on by integrating custom silicon to rework the balance between costs, power and performance.
The reason for this development is the sustained cost and supply challenge around HBM.
Large players like Nvidia can secure HBM parts with top-tier, but smaller companies or data centers often have to settle for lower speed modules.
This difference creates an uneven gaming field where access to the fastest memory directly forms competitiveness.
If D-Matrix can actually supply alternatives to lower costs and higher capacity, it would address one of the central pain points in the scaling inference at the data center level.
Despite the allegations of “10x better performance” and “10x better energy efficiency”, D-Matrix is still at the beginning of what it describes as a perennial journey.
Many companies have tried to tackle the so -called memory wall, yet few have transformed the market in practice.
The increase of AI tools and the dependence on all LLM shows the importance of scalable inference hardware.
Whether Popehawk and Corsair will mature to widely adopted alternatives or remain experimental to see.
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