- IBM pushes transistor density below the long-feared barrier of one nanometer
- NanoStack abandons flat chip layouts in favor of vertical transistor stacking
- The prototype delivered 50% more performance during IBM’s lab testing phases
IBM has unveiled what it describes as the world’s first sub-1nm chip technology, carrying nearly 100 billion transistors on a surface the size of a fingernail.
The breakthrough revolves around a new 3D NanoStack architecture that moves transistor scaling into the 0.7 nm or 7 angstrom era.
For context, today’s most advanced commercial chips typically sit around the 2nm mark, making this a significant jump in density.
Build upwards to keep Moore’s Law alive
The semiconductor industry has spent decades squeezing more transistors onto ever-smaller pieces of silicon to improve computer performance.
That process has become progressively more difficult as transistor dimensions approach the scale of just a few atoms across modern processors.
IBM’s approach avoids further horizontal compression by instead stacking transistor layers vertically through a three-dimensional nanosheet architecture.
The design packs nearly double the transistor density of IBM’s 2nm chip technology, introduced back in 2021.
According to the company, the architecture also delivers approximately 40% greater SRAM scaling to support increasingly demanding AI workloads.
This vertical method allows engineers to separate n-type and p-type transistors into different layers, which IBM says allows independent optimization of materials for each.
compared it to building a large block of flats rather than houses in a city.
“IBM’s NanoStack is like proposing a 100-storey skyscraper,” said Professor Alan Woodward, a computer scientist at Surrey University.
Using this analogy, IBM’s closest competitors, like Intel and Samsung, are somewhere around a 30 to 50-story building away from IBM.
In testing, the company reported a 50% performance improvement and 70% greater energy efficiency compared to its existing 2nm chips, along with a 40% gain in on-chip memory scaling.
Despite the performance improvements mentioned, the technology is still several years away from commercial use, and IBM estimates that production could begin within five years at the earliest.
“With our new NanoStack architecture, we’re not only making smaller transistors, we’re reinventing how chips are built to deliver dramatically more power and energy efficiency,” said Jay Gambetta, director of IBM Research and IBM Fellow.
The trade-offs behind the density increases
Vertical stacking introduces complications mostly around heat dissipation, as transistors generate heat that becomes more difficult to manage when they are close together.
The same narrow spacing also increases the effort of wafer alignment, as the layers must be bonded with extreme precision to avoid malfunctions.
Researchers acknowledge that when the gaps between the layers become too thin, transistors can fail to turn off properly, undermining the very density gain that the NanoStack is intended to provide.
These technical compromises are symptoms of a deeper problem facing the entire chip industry.
For decades, manufacturers have relied on Moore’s Law, in which the transistor pattern doubles roughly every two years.
But that pace has become harder to maintain as designs approach the physical limits of individual atoms.
Whether NanoStack actually extends this trajectory by another decade, as IBM projects, depends on whether these unsolved manufacturing challenges can be solved at scale.
It is partly for this reason that IBM has drawn in partners including ASML, Lam Research and Tokyo Electron, signaling an industry-wide effort behind this push toward angstrom-level scaling.
Still, similarly bold claims accompanied IBM’s 2nm chip unveiling in 2021, but turning lab success into mass production historically takes longer than initial announcements.
Via IBM
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