- Qualcomm introduces High Bandwidth Compute (HBC) memory architecture
- It utilizes a hybrid design that stacks LPDDR memory in a 3D space and utilizes multiple layers to essentially replace what the current generation of High Bandwidth Memory (HBM4) does
- The move, which leverages Qualcomm’s extensive experience with LPDDR, is not only power efficient, but also offers massive amounts of bandwidth and up to 768GB of stacked memory for AI workloads
Qualcomm is reviving its data center ambitions and building on its expertise as a chip designer that excels in the low-power computing segment by focusing on an entirely new architecture: High Bandwidth Compute (HPC).
The solution is a hybrid version of existing LPDDR memory that Qualcomm has successfully stacked in vertical 3D space, not unlike the industry standard High Bandwidth Memory (HBM) and its latest iteration, HBM4, while delivering significant power savings along the way.
The move is made possible by Qualcomm offering a near-memory compute architecture that combines memory with a compute-based die, with the former stacked vertically on top of the latter, effectively enabling up to 133 TB/s.
An AI memory offering for the future?
While the current industry standard, HBM4, is already widely used, Qualcomm’s promised offering is expected to appear in mid-2027 as part of the next-generation AI inference accelerator, AI250.
HBC Gen 1 offers a theoretical capacity of 768 GB, which HBM4 struggles to match, and Qualcomm’s published bandwidth of 133 TB/s is an achievement, as modern HBM4 solutions offer approximately 3.3 TB/s per stick at the higher end.
However, some of these bandwidth claims may be a bit of an unfair comparison, as while HBM4 delivers raw bandwidth, Qualcomm’s solution (and its theoretical speeds) may only be in play because it does much of the computing on-die, making for an apples-to-oranges comparison in some ways.
However, Qualcomm is scoring key wins with an AI industry increasingly obsessed with power, or rather, the lack of it, to continue many of their planned builds by touting its efficiency gains, where it claims somewhere between 6x the bandwidth per watts versus HBM for larger batch sizes and as much as 200x efficiency gains when it comes to combining small and large groups of aids.
Qualcomm’s partner list includes Meta and Microsoft, with the former’s multi-generation agreement to use Qualcomm’s processors for AI highlighted as a key win. Microsoft CEO Satya Nadela reassured investors by describing the software giant’s partnership with the chip designer across the PC, local AI and data center segments.
Given that Microsoft is increasingly looking to address the environmental footprint of its AI data center rollout, with its CEO already assuring stakeholders and the community that the Redmond-based tech giant aims to be mindful of the water and power footprints of both planned and future data centers, this makes efficiency an even more important theme of late.
However, Qualcomm’s solution to ‘eliminate the HBM tax’ does not exist in a vacuum; Competing solutions such as High Bandwidth Flash, backed by Samsung, SanDisk and SK Hynix, are also shaping up as potential competitors, focusing on a low-write, high-read situation that most AI inference workloads tend to be.
Perhaps more importantly, Qualcomm’s solution and the impressive numbers it offers do not yet have any third-party independent test results that could confirm its efficiency claims, even as Microsoft’s vote of confidence is seen as an important one for one of the most important players in the mobile SoC business as it prepares to take part in a growing but increasingly competitive data center in the coming decade.
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