- The Marvell Structera X 2404 allows the reuse of DDR4 without buying new DRAM
- Twelve DIMMs per controller provides 1.5 TB of physical memory capacity
- Memory compression effectively doubles usable capacity when using LZ4 at line speed
Hyper-scalers under pressure from rising memory prices could turn to discontinued DDR4 modules as a practical resource.
The Marvell Structera X 2404 is a CXL-based memory expansion designed to make the reuse of DDR4 modules viable at scale.
When operators install 128GB devices retrieved from retired systems, the controller delivers up to 1.5TB of physical capacity without the need for new DRAM.
Implementation layout of Structera X 2404
The Structera X 2404 fits into standard data center server racks as a PCIe-attached device instead of a traditional DIMM, acting as an external memory resource.
It supports four DDR4 channels and allows three DIMMs per channel, creating a total of twelve modules attached to a single controller.
This approach appeals to hyperscalers because of the large amounts of legacy modules saved from previous upgrade cycles.
It also reduces manufacturing requirements because only the controller, board and cable require manufacturing, not the DRAM itself.
The DDR4 model focuses on cost, but some operators need more performance than older modules can deliver.
The Structera X 2504 serves these environments and uses DDR5 RAM across four channels.
It connects through CXL 2.0 over PCIe Gen5 and delivers more bandwidth because it bypasses the CPU’s memory channels.
This design appeals to installations that require faster throughput while still seeking expansion beyond the limits of the processor’s DDR5 DIMM slots.
The outstanding capability in both devices is memory compression, which changes how capacity is delivered and priced.
Marvell uses LZ4 at line speed and it reports ratios between 1.8x and 2x during normal operation. This means that a capacity of 1.5 TB can be scaled to as much as 3 TB.
This approach allows hyperscalers to treat recycled DDR4 as a larger and cheaper pool than its physical size suggests.
It also reduces pressure on DDR5 supply chains because systems can rely on compressed expansion instead of buying additional modules.
That said, latency remains the biggest concern because independent testing under real workloads has yet to happen.
CXL already introduces extra latency, and compression adds more uncertainty when memory access becomes unpredictable.
Without third-party testing of random read latency, it’s still unclear whether these devices perform well under scattered access patterns.
Random reads affect many production systems, and slow responses can wipe out the benefits of increased capacity.
This uncertainty represents the biggest technical risk because latency determines whether the extension behaves like true memory or a slower level.
Via ServeTheHome
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