- AMDS MI400 APU LANDER IN 2026, GOING AI, HPC and Calculates Efficiency
- New design has two aids with eight XCDs that double the MI300’s density
- Multimedia IO dies Offoads IO tasks and can integrate Xilinx FPGA Tech
AMD’s instinct MI400 APU is ready to arrive in 2026 -Designed for AI, Machine Learning and HPC workload, MI400 will build on Team Red’s Chiplet -based modular architecture and is expected to increase the calculation density, effect and scalability.
It can also play a role in future super -computing projects, including a possible successor to El Capitan, but so far AMD has only confirmed that the MI400 will use CDNA “Next” architecture.
However a patch that updates the API -Header to Mes (Microengine Scheduler) V12, stained by Coelacanth’s dream (and reported by Videocardz), provides some insight into its chiplet configuration.
According to the patch, the MI400 will contain two active interposer -matrises (AIDS), each containing four accelerated calculation dots (XCDs), a total of eight XCDs. This doubles the XCD count per. Help compared to MI300. By integrating more calculation dies into fewer interposers, AMD could reduce latency time and improve efficiency while the data flow is critical of AI and HPC workloads.
However Coelacanth’s dream Points out, “If the MI400 follows a similar CPU complex matrix (CCD) and auxiliary partitioning like MI300, where some AIDS is dedicated to CPUs rather than accelerators, the maximum number of XCDs in some configurations may be limited to four, potentially potentially Reduction of the XCD counting compared to MI300A APU.
An exciting addition to the MI400 is Multimedia IO DIE (MID) that separates the multimedia engine from AIDS. The middle is likely to manage memory controls, media engines and interface logic, allowing the calculation values to focus on treatment tasks. The patches propose support for up to two mids, probably the allocation of one per. Help.
This new component could be AMD’s first integration of the DeSal/Xilinx FPGA technology in its accelerator lineup. In 2022, AMD announced that it planned to incorporate Xilinx’s FPGA-powered AI-inferent engine in its CPU portfolio. It can also be an alveo series Data Center Acceleration Card.
The patches also refer a register change table (RRMT), allowing firmware to direct register transactions to specific AIDS, XCDs or Mids.
AMD has not yet released any official reproductions or specifications for the MI400 series, but with the accelerator expected to launch in 2026, after the arrival of the instinct MI350 series (built on the CDNA 4 architecture) later in years soon.
