Next GEN AMD EPYC processor, the codename Venice is the first HPC product to use TSMCS N2 node -but I wonder if Apple was there first


  • AMD shows its first 2nm-Class Venice CPU DIE BUILT using TSMCS N2 KNODE
  • Venice, built on Zen 6, is targeted at workloads
  • AMD and TSMC hope to elaborate on their cooperation for future innovations

AMD has announced that it has produced the first 2NM class silicon for its next generation EPYC processor, the “Venice” codename, which is expected to be launched in 2026 as part of AMD’s 6th generation EPYC lineup.

Core Complex Die (CCD) is the first high-performance computer product that is taped and brought up using TSMC’s advanced N2 process technology.

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