Xcenas MX1 Computational Memory combines thousands of RISC-V-Kernes with CXL 3.2 and SSD TIING


  • Xcena introduced the MX1 Computational Memory with thousands of RISC-V-Kernes on FMS 2025
  • MX1 offers near-data treatment Reduction of CPU memory costs and enables Petabyte-Scale SSD supported extension
  • Product R controversy Includes MX1P this year and MX1S in 2026 that supports CXL 3.2

At the recent FMS 2025 event (formerly Flash Memory Summit, but now called Future of Memory and Storage to better fit the expanded focus), the South Korean startup removed the XCENA wrapping of its first product, MX1 Computational Memory.

MX1 is built on PCIE Gen6 and Compute Express Link 3.2 standard. By placing calculation directly next to the dram, the chip is able to reduce the cost of moving data back and forth between processors and memory.

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