- Apollo 2 Switch supports Gen 6.2 and CXL 3.1 inside a single hybridchip
- Xconn wants to redefine bandwidth borders but the results in the real world remain completely untested
- Intel and Xconn work together to test full-teat compatibility in PCIe-based ecosystems
Xconn Technologies is preparing to demonstrate what it describes as a fully integrated, end-to-end PCIE Gen 6.2 and CXL 3.1 solution on the upcoming future of memory and storage (FMS25) event.
The company places launch as a critical step towards addressing the results of AI and Data Center workload.
As with any early stage technology demo, the scalability and reliability of the real world are still open-ended questions.
Hybrid Switch with theoretical Flexibility
The company’s Apollo 2 -Switch will be at the heart of this disclosure -marketed as the industry’s first hybrid contact to support both PCI Gen 6.2 and CXL 3.1 within a single chip, it is said to simplify InterConnect -Design and improve scalability.
“Xconn is thrilled to bring PCIE Gen 6.2 and CXL 3.1 -SWIKES to market PCIE Gen 6.2 and CXL, with examples now available,” said Gerry Fan, CEO of Xconn Technologies.
“As the industry accelerates towards more memory -centric and performance -intensive architectures, our commitment is to allow customers the best in class.”
These benefits aim to reduce the complexity of data centers while enabling broader architectural flexibility.
Although technically promising, the actual benefit of such integration of performance results depends on the workload of production quality.
Xconn’s collaboration with Intel is also located as a major development, which according to Intel Senior Fellow Ronak Singhal, the partnership will help ensure that both software and hardware components interact evenly and offer “robust end-to-end solutions.”
Companies expect this effort to promote an interoperable environment for PCIE and CXL technologies.
Still, past experience in the industry suggests that successful validation often takes time and more than a demo cycle.
The upcoming demo shows Low Latens, high-band width-switching, which highlights the infrastructure’s readiness for applications such as AI/ML model training, cloud computing and composed infrastructure.
Xconn’s stand will reportedly have a fully standard-based setup, but until the benchmarks are released, it is difficult to determine how much improvement users can expect compared to existing PCIe Gen 5 implementations.
Xconn has also collaborated with Scaleflux to improve CXL 3.1 Interoperability for AI and Sky Infrastructure.
Although this indicates momentum, it does not confirm how well the solution is integrated with the kind of workload that is currently emphasizing today’s architectures.
The consequences for high -speed storage are important if the technology delivers.
With increasing demand for the largest SSD capabilities and the fastest SSD performance, PCIE Gen 6 could support faster data transfers between storage units and treatment units.
These theoretical gains must still be tempered with skepticism until field data confirms the effect.
Xconns Demo may well mark the beginning of the next chapter in AI hardware. But for now, it remains a preview, not a point of evidence.
Via TechPowerup
