- Cadence Tool helps the NVIDIA model Rubin GPU -stream requirements across billions of bicycles
- Early analysis will help NVIDIA improve chip effectiveness and power consumption
- Nvidia and AMD -hardware both contribute to Cadence Emulation and Prototyping Platform
Cadence Design Systems has created a dynamic power analysis tool designed to handle very large chip design, including Nvidia’s Rubin GPU, carrying more than 40 billion gates.
EENEWS Europe Reports The Software works on the Palladium Z3 emulator, allowing engineers with incredibly high accuracy, how energy is consumed across billions of bikes in just a few hours.
This is especially useful for AI accelerators such as Rubin, where the workloads vary widely and can emphasize different areas of the design at different times.
Addressing early bottlenecks
Power modeling is increasingly important as chips get bigger and energy requirements are rising.
Rubin could pull about 700W to a single matrix, with multi-chip configurations that consume up to 3.6 kW. By running early simulations, design team size networks can more precisely, see and address bottlenecks before the chip even reaches production.
EENEWS says Rubin is reported to demand a respin. It taped out with TSMC in June on its 3NM N3P process, but Nvidia is looking for further increasing performance in preparation for a match against AMD’s upcoming MI450.
This could delay the first ruby samples in 2026, although shipments are still expected to begin at the end of that year.
The Cadence DPA app plays a central role in navigating these challenges, EENEWS says. The emulator can allegedly handle up to 48 billion gates, supporting the estimation of chip level of tops and average in the flow.
This allows developers to balance performance with efficiency and at the same time limit the risk of delay from underpowered or large networks.
The Palladium Z3 platform even uses Nvidia’s Bluefield Data Processing Unit and Quantum Infiniband Networking to connect to the Protium X3 FPGA Prototype system.
The protium platform is based on AMD Ultrascal FPGAs that can run RTL models of design, enabling early software tests before silicon is available. In this way, both NVIDIA and AMD hardware are involved in supporting Rubin’s design cycle.
Cadence first introduced a DPA app in 2016, but the increasing complexity of AI processors has since made such tools important.
In Rubin’s case, the analysis and prototype platforms will help engineers control power needs on a scale that has not been seen before, and the experiences learned here are expected to filter down in consumer products as technology matures.
