- Huawei proposes the Tau Scaling Law as an alternative to slowing down Moore’s Law
- LogicFolding architecture reduces signal delay through vertically stacked semiconductor circuit designs
- Traditional shrinking of transistors faces growing physical and financial constraints across the semiconductor industry
For more than five decades, the semiconductor industry’s reliance on a simple and powerful prediction, Moore’s Law, which states that transistors on a chip double roughly every two years, has now hit serious physical and financial walls.
The global industry is facing a slower geometric scaling and the constant erosion of benefits for costs per unit. transistor.
This common challenge has forced every major player to search for a new way forward, and at the 2026 IEEE International Symposium on Circuits and Systems (ISCAS), Huawei’s He Tingbo proposed an alternative framework called the Tau (τ) Scaling Law.
A new guiding principle from Shanghai
According to Huawei, peers and colleagues have already nicknamed this approach “Her Law” in recognition of her leadership.
Instead of focusing on shrinking transistor dimensions, this principle prioritizes the reduction of signal propagation delay.
Huawei believes that compressing the time constant τ can drive ongoing development across semiconductors and electronic systems.
The key technological breakthrough that makes this new law possible is a technique called LogicFolding.
Traditional chip design lays out all electronic components in a flat 2D grid that limits how close circuitry can sit—and LogicFolding instead breaks down the physical limits of conventional circuit layouts by dramatically shortening critical-path wiring.
It reduces the resistive and capacitive loading that normally slows signal propagation between transistors.
The result is a systematic compression of the time constant τ at both circuit and chip levels simultaneously.
Huawei has abandoned the traditional 2D chip design in favor of a layered 3D architecture.
Think of this transition as moving from a single-story home to a multi-story building with efficient elevators—Huawei can now stack more planar circuits vertically, making room for more transistors while placing the core components closer together.
The shorter transmission distances between circuits directly improve frequency and overall performance.
Practical results and future ambitions
Huawei claims it has already mass-produced 381 chips using this new scaling law across various industries.
The upcoming Kirin chips, scheduled for launch in the fall of 2026, will be the first to adopt the LogicFolding architecture.
By 2031, the company expects its high-end designs to achieve a transistor density equivalent to 14 Å or 1.4 nm processes.
“We believe that openness and cooperation are the keys to driving continuous progress in the semiconductor industry,” said He Tingbo
“No single company can independently find all the answers along the path of the semiconductor revolution.”
Huawei has every incentive to project confidence, given their current limitations from access to advanced manufacturing tools from TSMC or purchasing Nvidia’s latest AI chips.
Whether the τ scaling law can actually surpass Moore’s law over the next decade is still an open question.
Competing firms will likely treat this announcement with measured skepticism until real hardware reaches neutral testing labs.
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