- Researchers have created a NAND-DRAM hybrid, inspired by older camera technology
- Indium Gallium Zinc Oxide also promises advantages over silicon
- For now, this is only a prototype that requires further work
Belgian semiconductor research hub imec has unveiled what it claims is the first 3D implementation of charge-coupled device (CCD) memory architecture, reviving technology we’ve already seen used before in digital cameras and camcorders, but for a completely different purpose.
With 3D CCD architecture, the researchers were able to break one of the biggest bottlenecks in AI computing today – the memory wall – where GPUs and accelerators spend more time waiting for data than processing it due to poor memory bandwidth and power efficiency.
The new design combines the speed and rewritability of DRAM with the density and efficiency of NAND to form a type of hybrid.
Old camera technology may actually lead to future generations of memory
CCD technology is nothing new – charge-coupled devices have long been used in digital cameras, broadcast video equipment, scientific imaging and even astronomy sensors, but CCDs have since been replaced by CMOS image sensors.
Traditionally, CCDs work by physically moving electrical charges between semiconductor gates, and the same principle applies to imec’s research to enable highly efficient memory movement.
Instead of arranging memory cells side by side on a flat plane, like conventional DRAM, the design stacks them vertically in the same way as 3D NAND, and this is important because DRAM’s limitations include leakage, higher manufacturing costs, and a reduction in how quickly density improvements occur.
The chips also replace silicon with IGZO (Indium Gallium Zinc Oxide), which promises lower leakage, longer data retention, easier low-temperature processing, and strong compatibility with close 3D stacking.
With this hybrid architecture, imec has already demonstrated successful charge transfer at transfer rates of more than 4MHz, but this is still very early stage technology and the prototype uses only a small number of stacked layers. In theory, it should be able to scale as well as NAND, with commercial chips now exceeding 200 layers.
CCD architecture appears to promise reduced wear mechanisms and endurance that may even exceed NAND, making it ideal for highly intensive applications across AI training clusters and inference servers.
“Unlike byte-addressable DRAM, our 3D CCD device is designed to provide block-level data access, which is better suited for modern AI workloads,” added Program Director for Storage Memory Maarten Rosmeulen.
“The potential of this CCD device to be used as a buffer memory lies in its ability to be integrated into a 3D NAND Flash string architecture – the most cost-effective way to achieve a scalable, high bit density that is estimated to go well beyond the DRAM limit.”
The research also details future plans for the promising architecture, positioning it as a CXL Type-3 device, or one that adheres to industry standards for connecting GPUs, CPUs and accelerators. This is an important consideration with hyperscalers now turning to CXL as AI models become too large for local GPUs alone.
As a prototype and research product, there are still plenty of hurdles to overcome, including thermal behavior, layer count scaling, and of course real-world integration, but if successful, the new hybrid architecture could seriously help reduce one of the biggest costs in AI infrastructure, DRAM.
Looking ahead, imec suggests that the next phase may involve an entirely new class of memory architecture rather than simply developing existing designs further.
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